Chip select CS also is AND ed with the input CLK to give internal clock C4.

By parallel format we mean that the data bits are present simultaneously on individual wires, one for each data bit as shown below.

The upper NAND gates serving D A D B D C are enabled, passing data to the D inputs of type D Flip-Flops Q A Q B D C respectively.

Three bits of data will load into Q A Q B D C at the same time.

Clock pulses will cause data to be right shifted out to SO on successive pulses.

Advantage Of Serial Processing Serial Data At

Parallel data at D A D B D C is converted to serial data at SO.

We could have made the active low SHIFTLD almost two clocks wide, low almost a clock before t 1 and back high just before t 3.

It is either shifted into another integrated circuit, or lost if there is nothing connected to SO.

This 1, which was originally present at Q A after t 1, is now present at SO and Q C.

They also allow serial connections to and from other ICs like microprocessors.

The manufacturer labels the data inputs A, B, C, and so on to H.

It is abbreviated from our previous terminology, but works the same: parallel load if low, shift if high.

Otherwise, this real part is the same as what we have looked at in detail.

Second, whenever M1 is asserted, as indicated by the 1 of C31 (arrow), the data is shifted as indicated by the right pointing arrow.

The 8-shift stages, as indicated by title SRG8, are identified by the external inputs A, B, C, to H.

In this case, we can conclude that the parallel data is loaded synchronously with the clock C3.

Thus, we expect to clock in data at SER when shifting as opposed to parallel loading.

If there was a bubble with the arrow this would have indicated shift on negative clock edge (high to low).

We have not looked at asynchronous loading of data up to this point.

Since none of this required the clock, the loading is asynchronous with respect to the clock.

SER input is a function of the clock as indicated by internal label 2D.

The OR gate inset shows that the clock is controlled by LDSH.

Internal M3 is a function of input MODE and G1 and G2 as indicated by the 1,2 preceding M3.